/*
 * Copyright (c) 2007 Xilinx, Inc.  All rights reserved.
 *
 * Xilinx, Inc.
 * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
 * COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
 * ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
 * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
 * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
 * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
 * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
 * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
 * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
 * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
 * AND FITNESS FOR A PARTICULAR PURPOSE.
 *
*/
//
//#include "arch/cc.h"
////#include "xio.h"
//#include "xparameters.h"
////#include "xintc_l.h"
//#include "xemaclite.h"
//#include "xtmrctr.h"
////#include "xtime_l.h"


#include "xintc.h"
#include "xexception_l.h"
#include "uart485rev0.h"

#define INTC_BASEADDR              XPAR_INTC_0_BASEADDR
#define TIMER_INTR_ID              XPAR_INTC_0_TMRCTR_0_VEC_ID

#define Uart485_DEVICE_ID      XPAR_UART485REV0_0_DEVICE_ID
#define Uart485_INT_IRQ_ID     XPAR_INTC_0_UART485REV0_0_VEC_ID

extern Xuint32 ReceiveCompleted;

void Uart485_Interrupt_Handler(void * baseaddr_p);

void platform_enable_interrupts()
{
    	XExc_mEnableExceptions(XEXC_NON_CRITICAL);
}


XIntc intc;

XStatus platform_setup_interrupts()//,XTmrCtr *TmrCtrInstancePtr)
{
	XIntc *intcp;
	intcp = &intc;
	int Status;
	
//			xil_printf("IicInstancePtr %x\n\r",IicInstancePtr);
//			xil_printf("TmrCtrInstancePtr %x\n\r",TmrCtrInstancePtr);
	Status = XIntc_Initialize(intcp, XPAR_XPS_INTC_0_DEVICE_ID);
	if (Status != XST_SUCCESS)
	{
		return XST_FAILURE;
	}
  
//	/*
//	 * Connect the iic device driver handler that will be called when an
//	 * interrupt for the iic device occurs, the handler defined above performs
//	 * the specific interrupt processing for the device.
//	 */
	
	Status = XIntc_Connect(intcp, Uart485_INT_IRQ_ID,
                           (XInterruptHandler)Uart485_Interrupt_Handler,
                           (void *)XPAR_UART485REV0_0_BASEADDR);
	if (Status != XST_SUCCESS)
	{
		return XST_FAILURE;
	}
//			xil_printf("IicInstancePtr->RecvBufferPtr %x\n\r",IicInstancePtr->RecvBufferPtr);

//    Status = XIntc_Connect(intcp, TIMER_INTR_ID,
//                           (XInterruptHandler)XTmrCtr_InterruptHandler,
//                           TmrCtrInstancePtr);
//			xil_printf("XIntc_Connect  TmrCtrInstancePtr %x\n\r",TmrCtrInstancePtr);
                           
	
	Status = XIntc_Start(intcp, XIN_REAL_MODE);
	if (Status != XST_SUCCESS)
	{
		xil_printf("XIntc_Start failed\n\r");
		return XST_FAILURE;
	}
	
	xil_printf("\t\tXIntc_Start \n\r");
	
	/*
	 * Enable the interrupts for the IIC device.
	 */
	/*
//	 * Enable the interrupts for the timer device.
//	 */
//	XIntc_Enable(intcp, TIMER_INTR_ID);

    /*
     * Enable the interrupt for the Uart485 device.
     */
    XIntc_Enable(intcp, Uart485_INT_IRQ_ID);
	 
	 
	/*
	 * Initialize the PPC exception table.
	 */
   	XExc_Init();
   	
	 /* Register the interrupt controller handler with the exception table.
	 */
	XExc_RegisterHandler(XEXC_ID_NON_CRITICAL_INT,
			     (XExceptionHandler) XIntc_InterruptHandler,
			     intcp);

//	setup_timer();
	return XST_SUCCESS;
}

void Uart485_Interrupt_Handler(void * baseaddr_p)
{
	Xuint32 baseaddr;
	Xuint32 IntrStatus;
	Xuint32 IpStatus;
	baseaddr = (Xuint32) baseaddr_p;
	
	IpStatus = UART485REV0_mReadReg(baseaddr, UART485REV0_INTR_IPISR_OFFSET);
//	xil_printf("\n\r  - !!!!!!!!Interrupt Code : 0x%08x \n\r", IpStatus);
	
	if((IpStatus& 0x1)	== 0x1)	// Rx Interrupt
	{
		UART485REV0_mWriteReg(baseaddr, UART485REV0_INTR_IPISR_OFFSET, 0x1);
		UART485REV0_mWriteSlaveReg0(XPAR_UART485REV0_0_BASEADDR,0, 0x00000000);
		UART485REV0_mWriteSlaveReg1(XPAR_UART485REV0_0_BASEADDR,0, 0x00000000);
		
		ReceiveCompleted = 0xFFFFFFFF;
//		xil_printf("\n\r  - !!!!!!!!rx Interrupt Code \n\r");
	}
	else if((IpStatus& 0x2)	== 0x2)  // Tx Interrupt
	{
		UART485REV0_mWriteReg(baseaddr, UART485REV0_INTR_IPISR_OFFSET, 0x2);
		UART485REV0_mWriteSlaveReg0(XPAR_UART485REV0_0_BASEADDR,0, 0x00000000);
		UART485REV0_mWriteSlaveReg1(XPAR_UART485REV0_0_BASEADDR,0, 0xffffffff);
		
		ReceiveCompleted = 0xEEEEEEEE;
//		xil_printf("\n\r  - !!!!!!!!tx Interrupt Code \n\r");
	}
	else
	{
		ReceiveCompleted = 0x0;
	}
}


